The present invention is related to delay matching circuits and, more particularly, to delay matching circuits useful for translating TTL-level clock signals into MOS logic level signals for a phase-locked loop circuit in an integrated circuit.
A phase-locked loop circuit is used typically to generate an accurate frequency. Often the reference frequency is carried by a signal which swings between different digital logic levels than the digital logic levels used by the phase-locked loop (PLL) circuit. A converter circuit must be used to convert the logic levels of the incoming signals to the logic levels used by the PLL. A typical conversion system is illustrated in FIG. 1. An incoming clock signal at TTL (transistor-transistor logic) levels is received at an input terminal 13. A TTL converter circuit 11 changes the logic levels of the incoming signals to those of the PLL circuit 10, in this case, MOS logic levels. The output signals of the PLL circuit are fed back to a delay circuit 12, which returns the PLL signals for phase comparison with the signals from the circuit 11. The PLL circuit 10 tries to match the phases of the two incoming signals.
For the PLL circuit 10 to accurately follow the phase of the input clock signal, the low-to-high propagation delay time T.sub.LH of both input signals to the PLL circuit 10 should be very closely matched to each other even as the rise time of the input clock signal varies.
The problem with existing circuits used for previous converter circuits 11 and delay circuits 12 of FIG. 1 has been that the T.sub.LH of these circuits do not necessarily match each other as the rise time of the input clock signal varies. The T.sub.LH of the TTL converter circuit 11 is related to the rise time of the input clock signal. On the other hand, the delay circuit 12, typically has an output signal having a T.sub.LH which is directly related to the rise time of the feedback output signal of the PLL circuit 10, not the input clock signal. This is not satisfactory.
The present invention provides for a delay matching circuit suitable for both converter circuit 11 and the delay circuit 12 so that the T.sub.LH of the output signals are invariant to changes in the rise times of the input clock signal and hence the T.sub.LH of the output signals remain matched. In this manner the PLL circuit can accurately track the phase of the incoming clock signal.